Variable gain circuit and radio apparatus using the same

ABSTRACT

A gain switching circuit comprises first and second gain stages connected in parallel between the input terminal and the output terminal, and a control unit for allowing the first and second gain stages to be selectively operative, wherein the first and second gain stages respectively include input sections in which input impedance values viewed from the input terminal are substantially equal to each other, and output sections in which output impedance values viewed from the output terminal are substantially equal to each other. By this configuration, a gain switching circuit and a radio apparatus using such a gain switching circuit adapted so that input/output impedance does not fluctuate are provided without implementing switching between gain stages.

BACKGROUND OF THE INVENTION

The present invention relates to a variable gain circuit for switching aplurality of gains and a radio apparatus using such the variable gaincircuit.

In order to broaden the dynamic range in a radio (wireless) apparatus,it is effective to control gain. In FIG. 1 showing a conventional radioreceiver, the receiver comprises, for example, an antenna 1 forinputting a receiving signal externally transmitted, a conventionalamplifier 10 for amplifying the receiving signal, a bandpass filter 2for passing through a predetermined frequency band of the receivingsignal, a frequency converter 3 for converting a frequency of thereceiving signal, a local oscillator 4 for outputting a localoscillating signal, and a signal processing unit for processing afrequency converted signal. In this case, the level of a signal inputtedfrom the antenna 1 diversely changes. If gain of the amplifier 10 is notvariable, distortion may take place with respect to an excessive inputsignal, and/or noise characteristic may become poor with respect to avery small input signal. Accordingly, it is desirable that the amplifierhas variable gain so as to make attenuation with respect to an excessiveinput signal, and to make amplification with respect to a very smallinput signal.

The amplifier 10 comprises an input terminal, first through n-thamplifier stages 12a-12n connected in parallel with one another, and anoutput terminal 16. Each amplifier stage 12 comprises an input sidematching circuit 13, a gain stage 14, and an output side matchingcircuit 15. Accordingly, respective stages are matched with an inputside and output side by the matching circuits 13 and 15 to finallysupply the optimum receiving signal for the signal processing unit 5.

Moreover, as shown in FIG. 1, the antenna 1 and/or filter 2, etc. aregenerally disposed before and after the amplifier 10. Since these parts(circuit components) are designed on the basis of a predeterminedcharacteristic impedance Z₀ (generally 50 ohms, and hereinafter thecharacteristic impedance is assumed to be 50 ohms), if the inputimpedance or the output impedance of the amplifier is not set to 50ohms, antenna and/or filter disposed before and after the amplifier donot exhibit desired performance. However, since generally theinput/output impedance of the amplifier itself is not in correspondencewith 50 ohms, matching circuits 13 and 15 as shown in FIG. 2 are used toconvert (change) the input impedance or the output impedance of theamplifier into 50 ohms.

Here, a typical matching circuit serves to convert a certain impedanceinto a desired impedance at a predetermined frequency. Accordingly, iffrequency changes, or input impedance or output impedance of theamplifier itself changes, it is difficult to maintain matching.

Hitherto, an electronic circuit for carrying out switching betweenplural gains is of a structure in which switching between gain stages ismade by switches, or is of a structure in which respective gain stagesare connected in parallel as shown in FIG. 1. When the switches areprovided to the amplifier 10, for example, switches 17 and 18 areconnected before the matching circuit 13 and after the matching circuit15, respectively.

The operation of the circuit shown in FIG. 1 will be first described. Inthe case where the gain is set to A1 in the circuit of FIG. 1, switchesSWout1 of the first stage (denoted by reference numerals 17 and 18) areturned ON, and other switches of other stages (denoted by referencenumerals 17 and 18) are all turned OFF. Similarly, in the case where thegain is set to A2 in the second stage, switches SWin2 (17) and SWout2(18) are turned ON, and other switches are all turned OFF in otherstages. Since this gain selecting method utilizes switches, elements forconstituting switch such as an FET (field effect transistor) arerequired in order that those switches are formed (configured) within anIC (integrated circuit). For this reason, it was necessary to use GaAsprocess or BiCMOS process of high cost. Further, there are alsoinstances where the characteristic of the entirety of the circuit mightbe degraded in dependency upon performance of the switch.

In addition, for the previously described reason, from a practical pointof view, it is necessary to prepare matching circuits (not shown) everyrespective gain stages. Since the matching circuit which is generallycomprised of passive elements takes large occupation area within IC,there also results the problem that the chip area would be increased.

On the other hand, in the case where switches are not integrated withinIC, switches of externally attached parts are used. However, whenexternally attached parts are used, there takes places the problem thatthe area is increased and/or the cost becomes high.

The operation of the circuit will not be described. In order to set thegain to A1 in the circuit, as shown in FIG. 1 only the first gain stageincluding amplifier 14 is turned ON and other gain stages are all turnedOFF. Similarly, in order to set the gain to A2, only the second gainstage including amplifier 14 is turned ON and other gain stages are allturned OFF. Since this gain selecting method does not use switch, it canbe realized even by inexpensive process having no FET like bipolarprocess. However, since the input and output impedance values of thecircuit change to much degree in dependency upon a gain stage of whichbias is turned ON (i.e., a selected gain stage), it is difficult toallow the input and output impedance values of the circuit to match witha desired impedance value even if which gain stage is selected.

Further, in circuits as shown in FIG. 1, characteristics of respectivegain stages fluctuate without conducting tracking (following) withrespect to variations (unevenness) of the process.

In the circuit adapted for carrying out switching between plural gains,in the case where gain switching is carried out by using switch,performance of the entirety of the circuit became poor in dependencyupon performance of the switch, or it was necessary to use GaAs processor BiCMOS process of high cost because a switch was used.

In addition, with respect to impedance matching, in the case whereswitch is used, it is necessary to provide different matching circuitsfor every respective stage, resulting in large chip area. On the otherhand, in the case where no switch is used, even if a particular gainstage is selected, it is difficult to match impedances which wouldresult in a constant (fixed) impedance.

SUMMARY OF THE INVENTION

With the above-described problems in view, an object of this inventionis to realize, by a cheap bipolar process, without use of switch, a gainswitching means adapted so that input and output impedance values of theamplifier do not change even if a particular gain stage is selected, andthat it is thus sufficient to provide matching circuits respectively onthe input side and on the output side.

A variable gain circuit according to this invention is characterized inthat, in gain stages connected in parallel, input impedance values ofcircuits nearest to the input side and output impedance values ofcircuits nearest to the output side are caused to be substantially thesame at all gain stages, thereby permitting input and output impedancevalues to be substantially constant even when what gain stage isselected.

Generally, depending on whether power is delivered to an electroniccircuit and whether no power is delivered thereto, magnitudes of theinput impedance and the output impedance of the electronic circuitgreatly change. Similarly, also depending on changes in supply states ofthe bias power or the bias current from a bias circuit for setting theoperating state of the electronic circuit, the input/output impedance ofthe circuit may fluctuate.

The variable gain circuit of this invention is adapted so thatpredetermined signal amplification factors are determined in accordancewith amplification factors of the amplifying sections of plural gainstage blocks to select any one of respective gain stage blocks, therebymaking it possible to obtain a desired amplification factor. In thiscase, since even if a particular gain stage is selected, only one gainstage is caused to be in ON state and other all gain stages are causedto be in OFF state, the input impedance and the output impedance of theentirety of the variable gain stage are always substantially constant(fixed) even if a particular gain stage is selected, i.e., irrespectiveof the gain stage selected. For this reason, it is unnecessary toindividually provide different matching circuits at respective gainstages. When one matching circuit is used as the entirety of thevariable gain circuit, it is possible to match with a desired impedanceeven if a particular gain stage block is selected.

As a result, the total number of matching circuits which generallyoccupy large area within the Integrated Circuit (IC) can be decreased.Thus, the chip area can be reduced as a whole. Moreover, since it ispossible to simultaneously realize the gain switching function and theimpedance matching function, without use of connection switch, gainswitching circuit can be put into practice even with relatively cheapprocess such as typical bipolar process.

As described above, in accordance with this invention, in a variablegain circuit having a plurality of gain stages, it becomes easy to matchimpedances with external circuits connected to the input side and theoutput side, and the number of matching circuits can be reduced.

In addition, since a switch for gain switching is not used, thisvariable gain circuit can be realized with an inexpensive process suchas typical bipolar process.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a view showing the configuration of a conventional radioreceiver;

FIG. 2 is a view showing the configuration of a conventional variablegain circuit and matching circuits on the input side and on the outputside thereof;

FIG. 3 is a view showing the fundamental configuration of a variablegain circuit of this invention;

FIG. 4 is a view for explaining the principle of the variable gaincircuit of this invention;

FIG. 5 is a view for explaining the principle of the variable gaincircuit of this invention;

FIG. 6 is a view for explaining the principle of the variable gaincircuit of this invention,

FIG. 7 is a view showing an example of the configuration of an elementcircuit of the gain stage of the variable gain circuit of thisinvention;

FIG. 8 is a view showing another example of the configuration of anelement circuit of the gain stage of the variable gain circuit of thisinvention;

FIG. 9 is a view showing an example of the configuration of a matchingcircuit used in the variable gain circuit of this invention;

FIG. 10 is a view showing an example of the configuration in which thevariable gain circuit of this invention is applied to a radio receiver;

FIG. 11 is a view showing the configuration of a first applicationexample of the variable gain circuit of this invention;

FIG. 12 is a view showing the configuration of a second applicationexample of the variable gain circuit of this invention;

FIG. 13 is a view showing the configuration of a third applicationexample of the variable gain circuit of this invention;

FIG. 14 is a view showing the configuration of a fourth applicationexample of the variable gain circuit of this invention;

FIG. 15 is a view showing the configuration of a fifth applicationexample of the variable gain circuit of this invention;

FIG. 16 is a circuit diagram showing a first circuit example of thevariable gain circuit according to the present invention;

FIG. 17 is a circuit diagram showing a second circuit example of thevariable gain circuit according to the present invention;

FIG. 18 is a circuit diagram showing a third circuit example of thevariable gain circuit according to the present invention;

FIG. 19 is an equivalent circuit diagram for explaining a principle ofthe present invention;

FIG. 20 is a characteristic diagram for explaining a principle of thepresent invention; and

FIG. 21 is a block diagram showing a configuration of a radio apparatusaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

There will be described a variable gain circuit and a radio apparatususing the same according to preferred embodiments the present inventionin reference with the attached drawings.

At first, before the description of the preferred embodiment, thefundamental configuration of the variable gain circuit of this inventionwill now be described with reference to FIG. 3. Reference numerals 20A,20B, . . . , and 20C denote plural different gain stage blocks. Inrespective gain stage blocks, input sections 21a, 21b, . . . , and 21n,amplifying sections 22a(A1), 22b(A2), . . . , and 22n(An), and outputsections 23a, 23b, . . . , and 23n, etc. are included.

As shown in FIG. 6, plural gain stage blocks are connected in a parallelfashion to thereby constitute a variable gain stage as a whole, and amatching circuit 13 of the input side and a matching circuit 14 of theoutput side are respectively connected before and after the variablegain stage.

In the above-mentioned fundamental configuration, an input circuitsection is constituted so that input impedance values of the circuitportions (input sections 21a, 21b, . . . , and 21n of the gain stageblocks 20A-20N) nearest to the signal input terminal 11 included in theindividual gain stage blocks 20A, 20B, . . . , and 20N are substantiallyequal to each other, and an output circuit section is constituted sothat output impedance values of the circuit portions (output sections23a, 23b, . . . , and 23n of the gain stage blocks 20A-20N) nearest tothe signal output terminal 12 are substantially equal to one another.When consideration is made in connection with the input impedance valuesand the output impedance values of the individual gain stage blocks, theinput impedance of the entirety of the variable gain stage is affectedto the maximum degree by input impedance values of the circuits nearestto the signal input terminal, i.e., the circuits of the input sectionsof respective gain stages, and the output impedance of the entirety ofthe variable gain stages is affected to the maximum degree by outputimpedance values of the circuit nearest to the signal output terminal,i.e. the circuits of the output sections of respective gain stages. Onthe contrary, input impedance values and output impedance values, etc.of the amplifying section circuits provided between the input sectionsand the output sections of the gain stage blocks have less influence onthe input impedance and the output impedance of the entirety of thevariable gain stage.

Generally, when power is delivered to an electronic circuit and when nopower is delivered thereto, magnitudes of the input impedance and theoutput impedance of the electronic circuit greatly change. Similarly,depending upon changes in supply states of the bias power or the biascurrent from a bias circuit for setting the operating state of theelectronic circuit, the input/output impedance of the circuit mayfluctuate.

The gain switching circuit of this invention is adapted so thatpredetermined signal amplification factors are determined depending uponamplification factors of the amplifying sections of plural gain stageblocks to select any one of respective gain stage blocks, thereby makingit possible to obtain a desired amplification factor. In this case, onlyone gain stage is caused to be in ON state and other all gain stages arecaused to be in OFF state, the input impedance and the output impedanceof the entirety of the variable gain stage are always substantiallyconstant (fixed) even if a particular gain stage is selected, i.e.,irrespective of the gain stage selected. For this reason, it isunnecessary to individually provide different matching circuits atrespective gain stages. When one matching circuit is used as theentirety of the gain switching circuit, it is possible to match with adesired impedance even if a particular gain stage block is selected.

As a result, the total number of matching circuits which generallyoccupy large area within the Integrated Circuit (IC) can be decreased.Thus, the chip area can be reduced as a whole. Moreover, since it ispossible to simultaneously realize the gain switching function and theimpedance matching function without use of connection switch, thevariable gain circuit can be implemented even with a relativelyinexpensive process such as a typical bipolar process.

The fundamental configuration of the variable gain circuit of thisinvention is shown in FIG. 3. Respective input impedance values ofcircuits nearest to the input side (input sections 21a, 21b, . . . , and21n) and output impedance values of circuits nearest to the output side(output sections 23a, 23b, . . . , and 23n) of respective gain stageblocks 20A, 20B, . . . , and 20N were caused to be substantially thesame at all gain stages, wherein a control unit 24 carries out selectionof gain stage block in accordance with a desired gain.

The reason for employing the configuration in which input impedancevalues are caused to be substantially the same will now be describedwith reference to FIGS. 4 and 5. For the brevity of explanation, it isassumed that consideration is made in connection with two circuits, andit is further assumed that one input impedance is Zin and the otherinput impedance is Zin. Initially, as shown in FIG. 4, a matchingcircuit 25 adapted to allow impedance to match with the characteristicimpedance 50 ohms is connected to two circuits 26 and 26 of inputimpedance Zin connected in parallel. When there results such a state, noreflection of an input signal at the input terminal takes place.

Then, as shown in FIG. 5, a matching circuit 25 is connected to acircuit comprising a circuit 26 of input impedance Zin and a circuit 27of input impedance Zin' connected in parallel. Here, if this circuitarrangement has an input impedance Zm such that the voltage standingwave ratio (VSWR) at the input terminal is expressed as "VSWR<3", sincepower reflected at the input terminal is less than one half, Zin andZin' are considered to be substantially the same impedance.

In the case where the gain stage 20A is selected in the circuit of FIG.3, the control unit 24 is caused to be operative so that only the gainstage 20A is turned ON and other gain stages 20B-20N are all turned OFF.At this time, the gain of the circuit of FIG. 3 is expressed asAin+A1+Aout dB!. Moreover, the input impedance and the output impedanceof this circuit are substantially determined by the input impedancevalues of circuits nearest to the input side and the output impedancevalues of circuits nearest to the output side of respective gain stages.In the case of the circuit of FIG. 3, only one gain stage selected ofthe circuits nearest to the input side of respective gain stages is inON state, and circuits of other gain stages are all in OFF state. Inputimpedance of the circuit of FIG. 6 is equal to a value when inputimpedance (Zon) of one input side circuit in ON state denoted byreference numeral 28 and input impedance (Zoff) of (n-1) input sidecircuits in OFF state denoted by reference numeral 29 are connected inparallel. This state is the same regardless which gain stage isselected, i.e., irrespective of gain stage selected, the input impedanceof the circuit of FIG. 3 is fixed (constant).

This similarly applies to the output side. Since only the selected gainstage is in ON state and other gain stages are in OFF state, the outputimpedance is constant at all times. For this reason, it is sufficientthat matching circuits are the same regardless of which gain stage isselected in the circuit of FIG. 3, it is enough to respectively providematching circuits on the input side and on the output side. Therefore,it is unnecessary to prepare a large number of matching circuits as inthe case of the circuit shown in FIG. 1.

Individual circuits at respective gain stages of FIG. 3 may be, e.g., anemitter-grounded amplifier 30 as shown in FIG. 7, or may be anattenuator 31 in which resistance elements 32a-32c are connected in πform as shown in FIG. 8. The circuit form, the magnitude of gain, andmagnitude of quantity of attenuation are arbitrary. Generally,dimensions of these circuits are about 100 μm² at the best. On the otherhand, in a matching circuit using typical passive element in which acapacitor 33 and an inductor 34 are connected in series as shown in FIG.9, the inductor 34 and capacitor 33 respectively have great area morethan several hundreds μm² and 100 μm². Accordingly, in the case of thecircuit of FIG. 3, since only circuits less than 100 μm² are onlyprovided in respective stages, the number of matching circuits whichoccupy large area can be reduced, and the chip area can be reduced.

Moreover, FIG. 10 shows an example where the circuit of FIG. 3 is usedas a radio receiver 35. A receiving signal inputted from an antennasection 1 is converted into a base band signal by a frequency converter3 through a band-pass filter 2. The base band signal thus obtained isconverted into speech/picture data, etc. by a signal processing unit 5.The signal processing unit 5 judges magnitude of signal amplitude. Inthe case where the signal processing unit 5 detects changes(fluctuation) of the level of a receiving signal, it outputs a controlsignal to control unit (not shown) of a variable gain circuit 36 in themanner of having the above-mentioned configuration or the like. When theradio receiver receives, e.g., a signal of amplitude value of apredetermined level or more, the signal processing unit 5 outputs acontrol signal to allow quantity of attenuation of signal amplitude tobe large. In the case where the signal processing unit 5 cannot detect asignal of amplitude value of a predetermined level, it outputs a controlsignal to allow attenuation quantity of signal amplitude to be small.

In the gain switching circuit using this invention, since the inputimpedance and the output impedance both match with 50 ohms, antennaand/or filter disposed before and after the gain switching circuitindicate satisfactory characteristics, and there results no unnecessaryreflection taking place.

The circuit shown in FIG. 11 is of a structure comprising gain stageblocks 20A, 20B, . . . , and 20N connected in parallel so that outputimpedance values of circuits nearest to the output side (output sections23a, 23b, . . . and 23n) of respective gain stage blocks 20A, 20B, . . ., and 20N are caused to be equal to each other at all the gain stages.In order to select gain stage 20A in this circuit, only the gain stage20A is caused to be turned ON, and other all gain stages are caused tobe turned OFF. Thus, the output impedance of the circuit of FIG. 11becomes equal to a value when output impedance of one circuit nearest tothe output side in ON state and output impedance of (n-1) circuitsnearest to the output side in OFF state are connected in parallel.Accordingly, the output impedance is constant (fixed) even if aparticular gain stage is selected.

Similarly, in the circuit of FIG. 12, the input impedance becomesconstant even if any of gain stages 20A, 20B, . . . , or 20N areselected. Namely, circuits nearest to the input side (input sections21a, 21b, . . . , and 21n) of respective gain stage blocks 20A, 20B, . .. , and 20N are adapted so that input impedance values are equal to eachother at all gain stages and are used to provide a configurationcomprising these circuits connected in parallel so that the inputimpedance becomes constant.

Variations (Unevenness) of the manufacturing process of thesemiconductor will not be considered. In a circuit as shown in FIG. 3,variations in the input impedance or the output impedance of respectivegain stages individually take place at respective gain stage blocks.Accordingly, the input impedance or the output impedance of the entiretyof the circuit shown in FIG. 3 would vary in accordance with which gainstage is selected. On the contrary, the circuit including gain stageblocks 40A, 40B, . . . , 40N shown in FIG. 13 is of a structure in whichcircuits nearest to the input side (input sections 41a, 41b, . . . , and41n) and circuits nearest to the output side (output sections 43a, 43b,. . . , and 43n) of all gain stage blocks 40A, 40B, . . . , and 40N arecaused to have the same circuit configuration and the same circuitconstants. When such an approach is employed, input impedance values ofthe circuits nearest to the input side and output impedance values ofthe circuits nearest to the output side vary (fluctuate) while carryingout tracking with respect to variations of the process. For this reason,irrespective of gain stage selected, the input impedance and the outputimpedance of the entirety of the circuit shown in FIG. 13 becomeconstant. Numerals 42a, 42b, . . . , 42n denote amplifying sections inthe gain stage blocks 40A, 40B, . . . , 40N.

In the circuit shown in FIG. 14, circuits nearest to the input side(input sections 44a, 44b, 44c, . . . , and 44n) and circuits nearest tothe output side (46a, 46b, 46c, . . . , 46n) of all gain stage blocks(45A, 45B, 45C, . . . , and 45N) are caused to have the same circuitconfiguration and the same circuit constants, the portions except forthe above are respectively constituted by using the same circuits, anddifferences between gains prescribing amplification factors ofrespective gain stages are determined by varying the number of stages ofcircuits connected. With respect to the input impedance and the outputimpedance of this circuit, similarly to the case of the circuit of FIG.13, they are constant regardless of which gain stage is selected.Moreover, in FIG. 14, the gain difference between gain stage 45A andgain stage 45B becomes equal to magnitude A of unit gain of unit gainblock 47a, . . . , or 4 mn, and gain difference between gain stage 45Band gain stage 45C also becomes equal to A. Namely, with respect tovariations of the process, characteristics of individual circuitsconstituting respective gain stages change while carrying out tracking.For this reason, gain differences between respective gains stages becomeequal to A. With respect to gain differences between respective gainstages, it is possible to precisely provide gain differences by the stepof magnitude A of unit gain at all times. Accordingly, the final gainstage block 45N includes intermediate gain section 47n through 4 mn at mstages.

Moreover, the circuit of FIG. 15 is adapted so that circuits nearest tothe input side (51a, 51b, 51c, . . . , and 51n) and circuits nearest tothe output side (53a, 53b, 53c, . . . , and 53n) of all gain stageblocks 50A, 50B, 50C, . . . , and 50N are caused to have the samecircuit configuration and the same circuit constants, portions ofamplifying sections 52a, 52b, . . . , and 52n are respectivelyconstituted by using circuits of the same configuration, and differenceof gains between respective gain stages are determined by prescribing away of giving bias current delivered to the circuits of the amplifyingsections. That is, the gain stage blocks 50A-50N respectively comprisecurrent sources 54a, 54b, . . . , 54n. Accordingly, when sizes ofdevises, e.g., transistors used in current sources for determining biascurrents are changed to determine bias values of respective gain stages,values of biases of respective gain stages fluctuate while carrying outtracking with respect to variations. In this case, since gain of theamplifier is generally proportional to bias, it is possible to keepconstant gain differences between respective gain stages of the circuitof FIG. 15 similarly to the case of the circuit of FIG. 14.

Next, there will be described a detailed circuit configuration of eachtype of the variable gain circuits in accordance with FIGS. 16 through18.

FIG. 16 is a circuit diagram showing a variable gain circuit accordingto a first concrete example including a matching circuit on an inputterminal side. The variable gain circuit of the first examplecorresponds to the circuit shown in FIG. 12, and comprises an input sidematching circuit 13, and a plurality of gain stage blocks 20A through20N. The gain stage block 20A comprises an input amplifier section 21a,capacitors Ca1 and Ca2, and an amplifier section 22a, and the gain stageblock 20N comprises an input section 21n, capacitors Cn1 and Cn2, and anattenuator section 22n. The matching circuit 13 is comprised of an LCcircuit.

In the above configuration, since the input amplifier stages of thefirst through N-th gain stage blocks have the same configuration, theamplifier stages 21a through 21n have the same input impedance valueviewed from the input terminal 11. Since the circuit 22a is theamplifier and the circuit 22n is the attenuator, both the circuitsgenerally have different output impedance value, respectively.Accordingly, in this example, an impedance matching is performed only onthe input side in accordance with the present invention.

FIG. 17 is a circuit diagram showing a variable gain circuit accordingto a second concrete example including a matching circuit on an outputside. The variable gain circuit of the second example corresponds to thecircuit shown in FIG. 11, and comprises a plurality of gain stage blocks20A through 20N connected in parallel with one another, and an outputside matching circuit 14. The first gain stage block 20A comprises aninput stage 21a, amplifier stage 22a and output stage 23a, and the N-thgain stage block 20N comprises a section 21n, 22n and 23n. The matchingcircuit 14 is also comprised of an LC circuit.

FIG. 18 is a circuit diagram showing a variable gain circuit accordingto a third concrete example including matching circuits on both inputand output sides. The variable gain circuit of the third examplecorresponds to the circuit shown in FIG. 3, and comprises matchingcircuits 13 and 14, and a plurality of first through N-th gain stageblocks 20A through 20N. The first gain stage block 20A comprises aninput stage 21a, amplifier stage 22a and output stage 23a, andcapacitors Ca1 and Ca2. The N-th gain stage block 20N comprises an inputstage 21n, attenuator stage 22n and output stage 23n, and capacitors Cn1and Cn2. The matching circuits 13 and 14 are respectively comprised onan LC circuit.

Here, there is described a schematic operation of the variable gaincircuit according to the second example with reference to FIGS. 19 and20. FIG. 19 is an equivalent circuit diagram of the gain circuit shownin FIG. 17. In FIG. 19, the gain stages are comprised of the first andsecond gain stages which respectively have a dynamic range as follows.

Generally, the lower limit of the dynamic range of the amplifier isdetermined by a noise characteristic, and the upper limit of the dynamicrange is determined by a distortion characteristic when the amplifierincludes active elements (transistors). Accordingly, when the gaincircuit is comprised of an active element such as the amplifier stageblock 20A shown in FIG. 17, the block 20A has a dynamic range between-100 dBm and -25 dBm without noise and distortion characteristics of theamplifier. Here, the amplifier 23n shown in FIG. 19 has the dynamicrange from -100 dBm to -25 dBm as a single body.

On the other hand, when the signal is attenuated by the attenuator stageblock 20N having a π type resistors, as shown in FIG. 19, the attenuator20N attenuates the signal level with 20 dB from an input signal having-100 dBm which is originally sufficient to an amplifier single body, sothat the signal level is buried in the noise level, thereby disablingthe receiver to receive the input signal. Accordingly, when theattenuator is provided at the initial stage such as the circuit FIG. 17(FIG. 19), the dynamic range becomes narrower with an attenuatedcomponent, that is, 20 dB.

On the contrary, when the large amount of the signal power is supplied,it is advantageous with the attenuated component by the initial stageattenuator. For example, even though the signal having the level of -25dBm which is a limit value receivable to the amplifier single bodywithout distortion is supplied, it is possible to receive the signalwith a predetermined margine because the attenuator attenuates thesignal level with 20 dB. Accordingly, the upper limit of the dynamicrange seems to be broadened with an attenuated amount of the attenuator.This principle can be shown in FIG. 20.

Here, in a personal handyphone system (PHS) for example, the dynamicrange is required for the signal reception from -100 dBm to +5 dBm.

Accordingly, if -25 dBm is the original upper limit of the dynamic rangein the amplifier, 30 dB is necessary as the attenuated amount to receivethe signal of +5 dBm in accordance with the following equation:

    -25-5=-30 (dB).

Therefore, the attenuation amount is necessary for about 30 dB. However,since the amplifier block and attenuator block respectively have thedifferent distortion and noise characteristics and attenuator block hasan extreme distortion characteristic, the upper limit of the dynamicrange is improved. Accordingly, 20 dB may be attenuated actually toobtain the sufficient signal reception.

The stage number of the variable gain stage blocks is generally twostages, the difference of the individual stages may be sufficient to beabout 30 dB. When the variable gain circuits is configured in themultistage blocks, proper margines are provided between the adjacent twoblocks, respectively.

Finally, there is described a radio apparatus according to a preferredembodiment of the present invention with reference to FIG. 21. In FIG.21, the duplicated description will be omitted with respect tocomponents having the same numerals in FIG. 1.

The radio apparatus 60 comprises an antenna 1, a low noise amplifier 61,band-pass filter 62. Variable gain circuit 20, band-pass filter 2,frequency converter 3, local oscillator 4, and signal processing unit 5.It is possible for such a constitution to obtain the optimum receptionsignal by changing over the optimum gain by the variable gain circuit.The low noise amplifier 61 and band-pass filter 62 may constitute areception circuit for receiving the input signal through the antenna 1.

What is claimed is:
 1. A radio apparatus adapted for receiving data byperforming a frequency conversion of a receiving signal from a radiofrequency into a base band frequency to perform a predetermined signalprocessing, said apparatus at least comprising:an input terminal; anoutput terminal; a plurality of gain stages directly connected inparallel between said input terminal and said output terminal; andsignal processing means for controlling a change-over from one of theplurality of gain stages to another of the plurality of gain stagescorresponding to said receiving signal of the radio frequency.
 2. Theradio apparatus according to claim 1, whereinan input impedance value ofone of the plurality of gain stages viewed from said input terminal issubstantially equal to another input impedance value of another of theplurality of gain stages connected in parallel.
 3. The radio apparatusaccording to claim 1, whereinan output impedance value of one of theplurality of gain stages viewed from said output terminal issubstantially equal to another output impedance value of another of theplurality of gain stages connected in parallel.
 4. The radio apparatusaccording to claim 1, whereinan input impedance value of one of theplurality of gain stages viewed from said input terminal issubstantially equal to another input impedance value of another of theplurality of gain stages connected in parallel, and an output impedancevalue of one of the plurality of gain stages viewed from said outputterminal is substantially equal to another output impedance value ofanother of the plurality of gain stages connected in parallel.
 5. Theradio apparatus according to claim 1, whereinsaid radio apparatusfurther comprises a signal power detection means for detecting signalpower of said receiving signal of said radio frequency; and said signalprocessing means controls said change-over corresponding to said signalpower of said receiving signal of the radio frequency.
 6. The radioapparatus according to claim 5, whereinsaid signal power detection meansfurther comprises an amplitude detection means for detecting anamplitude value of said receiving signal of the radio frequency; andsaid signal processing means controls said change-over corresponding tosaid amplitude value of said receiving signal of the radio frequency. 7.A variable gain circuit comprising:an input terminal; an outputterminal; a plurality of gain stages directly connected in parallelbetween the input terminal and the output terminal; a control unit forallowing said plurality of gain stages to be selectively operative; aninput side matching circuit having an input side, an input impedancevalue viewed from said input side and representing an input impedance ofthe variable gain circuit, and an output connected in series to saidinput terminal; and an output side matching circuit having an inputconnected in series to said output terminal, an output side, and anoutput impedance value viewed from said output side and representing anoutput impedance of the variable gain circuit.
 8. The variable gaincircuit according to claim 7, wherein each of said plurality of gainstages comprises:an input stage for inputting a high frequency signal;at least one amplifier stage, connected in series to said input stage,for outputting an amplified signal; and an output stage, connected inseries to said at least one amplifier stage.
 9. The variable gaincircuit according to claim 7, wherein the input impedance value issubstantially the same regardless of which of the plurality of gainstages are operative.
 10. The variable gain circuit according to claim7, wherein the output impedance value is substantially the sameregardless of which of the plurality of gain stages are operative.
 11. Avariable gain circuit comprising:an input terminal; an output terminal;a plurality of gain stages, directly connected in parallel between theinput terminal and the output terminal, each having an input stage, atlest one amplifier stage, and an output stage connected in series; and acontrol unit for allowing said plurality of gain stages to beselectively operative; wherein each output stage of the plurality ofgain stages is caused to have substantially the same circuitconfiguration and substantially the same circuit constants as any otherof the plurality of gain stages, such that an input impedance viewedfrom said input terminal remains substantially the same regardless ofwhich of the plurality of gain stages are operative; and wherein eachoutput stage of the plurality of gain stages is caused to havesubstantially the same circuit configuration and substantially the samecircuit constants as any other of the plurality of gain stages, suchthat an output impedance viewed from said output terminal remainssubstantially the same regardless of which of the plurality of gainstages are operative.